RTL Design Lead

Ovii's Interpretation of the Role

We’re looking for an RTL Design Lead to drive RTL development for complex ASIC/SoC projects in our Noida semiconductor team. You’ll own block‑level RTL creation, integration, and verification while mentoring junior engineers and collaborating across architecture, DFT and physical design.

Role Snapshot

• Lead RTL development for ASIC/SoC
• Define micro‑architecture with architecture team
• Drive block‑level integration, lint, CDC, synthesis
• Debug simulation and silicon bring‑up issues
• Mentor junior engineers
• Collaborate with DFT, Physical Design, Verification

Must-Have Requirements

• RTL design for ASIC/SoC
• Verilog/SystemVerilog
• AMBA protocols (AXI/AHB/APB)
• Synthesis
• Lint
• Clock domain crossing (CDC)
• Low‑power design methodologies
• Debugging and problem‑solving

Nice-to-Have Signals

• Prior team handling or technical leadership experience
• team handling
• technical leadership

Work Setup

• Location: Noida, India
• Work mode: ONSITE
• Employment type: Full-Time

Not Specified in JD

• Visa sponsorship
• Salary range
• Remote eligibility
• Education requirement
• Relocation

What You'll Likely Work On

• Lead end‑to‑end RTL development for complex ASIC/SoC blocks
• Partner with architecture and verification teams to define implementation strategies
• Perform block‑level integration, linting, CDC analysis, and synthesis
• Debug and resolve issues across simulation, synthesis and silicon bring‑up
• Coordinate with DFT, physical design and verification groups
• Guide and mentor junior RTL engineers
• Ensure design quality and on‑time delivery

Good Fit If You Have

• Prior experience leading or managing a small RTL team
• Strong problem‑solving mindset for hardware debugging
• Familiarity with low‑power design flows
• Comfort collaborating across cross‑functional hardware groups