Physical Verification Engineer

Ovii's Interpretation of the Role

We seek a Physical Verification Engineer to lead full‑chip and block‑level verification for advanced semiconductor nodes. The role involves DRC/LVS/ERC sign‑off, debugging layout violations, and building automation scripts while collaborating with design and foundry teams.

Role Snapshot

• Physical verification sign‑off
• DRC/LVS/ERC/ANT/Density/DFM debugging
• Automation scripting (Tcl/Perl/Python)
• Mentor Calibre tool expertise
• Advanced node support (≤5nm)
• Collaboration with design & foundry teams

Must-Have Requirements

• 5+ years of Physical Verification experience
• Strong expertise in DRC, LVS, ERC, ANT, Density, DFM, and sign‑off
• Hands‑on experience with Mentor Calibre or equivalent PV tools
• Good understanding of IC layout, CMOS process, and semiconductor manufacturing
• Experience with advanced technology nodes (16nm/7nm/5nm or below)
• Scripting knowledge in Tcl, Perl, or Python
• Strong debugging, analytical, and problem‑solving skills
• Physical verification sign‑off
• DRC/LVS/ERC/ANT/Density/DFM expertise
• Mentor Calibre tool usage
• Automation scripting
• BE/B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or related discipline

Nice-to-Have Signals

• Experience with PERC verification
• Exposure to ESD/Latch‑up verification
• Familiarity with FinFET technology and foundry sign‑off flows
• Knowledge of physical design flow and tapeout methodology
• PERC verification
• FinFET technology exposure
• Foundry sign‑off flow experience

Work Setup

• Location: Bengaluru, India
• Work mode: ONSITE
• Employment type: Full-Time

Not Specified in JD

• Visa sponsorship
• Salary range
• Remote eligibility
• Notice period
• Travel requirement

What You'll Likely Work On

• Execute block‑level and full‑chip physical verification sign‑off using Calibre or comparable tools
• Identify and resolve DRC, LVS, ERC, ANT, density, and DFM violations
• Run PV flows across multiple technology nodes (28nm‑5nm and below)
• Develop and maintain automation scripts in Tcl, Perl, or Python to streamline verification
• Partner with Physical Design, Layout, and Foundry teams to ensure clean tapeout
• Document verification results and support sign‑off reviews

Good Fit If You Have

• Experience with PERC and ESD/Latch‑up verification
• Exposure to FinFET technology and foundry sign‑off flows (TSMC, Samsung, Intel, GlobalFoundries)
• Familiarity with physical design flow and tapeout methodology