DFT Engineer | Noida | 5+

Ovii's Interpretation of the Role

We are looking for a Design‑for‑Test (DFT) Engineer to own scan insertion, ATPG generation and coverage closure for semiconductor products. You will collaborate across design, verification and ATE teams to deliver test patterns and support silicon bring‑up.

Role Snapshot

• Design‑for‑Test (DFT) Engineer
• Scan insertion & ATPG
• Coverage analysis & closure
• ATE pattern generation
• Collaboration with design & verification
• Silicon bring‑up support

Must-Have Requirements

• Scan insertion
• ATPG generation
• Coverage analysis
• MBIST insertion
• Boundary Scan
• TAP Controller
• IEEE 1500
• RTL and netlist DFT flows
• Perl scripting
• TCL scripting
• DFT engineering
• scan insertion
• ATPG
• BE/BTech/ME/MTech

Nice-to-Have Signals

• Static Timing Analysis (STA) exposure
• Exposure to DFT tools from Synopsys, Cadence, Siemens
• STA exposure

Work Setup

• Location: Noida, India
• Work mode: ONSITE
• Employment type: Full-Time

Not Specified in JD

• Visa sponsorship
• Salary range
• Remote eligibility
• Notice period
• Travel requirements
• Security clearance
• Coding test

What You'll Likely Work On

• Drive DFT insertion, ATPG generation, coverage closure and pattern validation across RTL and gate‑level flows
• Analyze and improve scan coverage to meet closure targets
• Develop and validate test patterns for ATE, including TDL generation
• Debug scan, ATPG and simulation issues during tape‑out and silicon bring‑up
• Collaborate closely with design, verification, physical design, STA and ATE teams
• Support DFT activities through silicon bring‑up and post‑silicon validation

Good Fit If You Have

• Familiarity with static timing analysis tools
• Exposure to DFT tools from Synopsys, Cadence or Siemens Mentor
• Experience scripting in Perl or TCL
• Background in semiconductor industry